Technical Event
Tuesday Plenary
25 February 2025 • 8:20 AM - 10:00 AM PST | Conv. Ctr., Grand Ballroom 220A
Session Chairs: Qinghuang Lin, Canon (United States) and John Robinson, KLA (United States)
8:20 AM - 8:40 AM:
Presentation of New SPIE Fellows
8:40 AM - 9:20 AM:
Strategic directions for electronics packaging
Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in Artificial Intelligence and Machine Learning that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of “scale-down and scale-out” that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. While, we have made progress towards this goal, the technologies we have developed have ridden on legacy packaging technologies making such systems incredibly complex and expensive to build. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically. There are many challenges in this approach. In this talk we will outline these challenges especially in lithography and die placement and show that the adoption of silicon like technology, new cooling and power delivery, large area lithography approaches, as well as design enablement will propel packaging into the next dimension.
Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. Till recently, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging Manufacturing Program, where he laid the foundational strategy for the national packaging imperative. He is the founding Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. Since joining UCLA, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He is a fellow of IEEE, APS, iMAPS and NAI as well as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPS distinguished educator award in 2021. Prof. Iyer was also Prof. Ramakrishna Rao Visiting Chair Professor at IISc, Bengaluru.
9:20 AM - 10:00 AM:
Abstract to be announced
Heike Riel is IBM Fellow, Head of Science of Quantum and Information Technology and Lead of IBM Research Quantum Europe at IBM Research. She is responsible for leading the research agenda of the Science of Quantum and Information Technology department aiming to create scientific and technological breakthroughs in Quantum Computing, Physics of Artificial Intelligence, Nanoscience and Nanotechnology, Precision Diagnostics and Smart System Integration.
She is a distinguished expert in nanotechnology and nanosciences and focuses her research on advancing the frontiers of information technology through the physical sciences. She contributed to advancements in the science and technology of nanoscale electronics, in particular the exploration and development of semiconducting nanowires and nanostructures for applications in future electronic and optoelectronic devices, in molecular electronics for future nanoscale switches and memory applications, and organic light-emitting diodes for display applications. Her current research interests include new materials and device concepts for future nanoelectronics for applications in quantum computing and neuromorphic computing. She also serves as the Deputy Director of the new Swiss National Competence Center for Research on Silicon Spin Qubits.
Event Details FORMAT: General session with live audience Q&A to follow each presentation.
MENU: Coffee, decaf, and tea will be available outside presentation room.
SETUP: Theater style seating.
8:20 AM - 8:40 AM:
Presentation of New SPIE Fellows
8:40 AM - 9:20 AM:
Strategic directions for electronics packaging
 |
Subramanian S. Iyer
UCLA Center for Heterogeneous Integration and Performance Scaling, Samueli School of Engineering (United States) |
Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in Artificial Intelligence and Machine Learning that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of “scale-down and scale-out” that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. While, we have made progress towards this goal, the technologies we have developed have ridden on legacy packaging technologies making such systems incredibly complex and expensive to build. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically. There are many challenges in this approach. In this talk we will outline these challenges especially in lithography and die placement and show that the adoption of silicon like technology, new cooling and power delivery, large area lithography approaches, as well as design enablement will propel packaging into the next dimension.
Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. Till recently, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging Manufacturing Program, where he laid the foundational strategy for the national packaging imperative. He is the founding Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. Since joining UCLA, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He is a fellow of IEEE, APS, iMAPS and NAI as well as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPS distinguished educator award in 2021. Prof. Iyer was also Prof. Ramakrishna Rao Visiting Chair Professor at IISc, Bengaluru.
9:20 AM - 10:00 AM:
 |
Heike Riel
IBM Research Frontiers Institute (Switzerland) |
Abstract to be announced
Heike Riel is IBM Fellow, Head of Science of Quantum and Information Technology and Lead of IBM Research Quantum Europe at IBM Research. She is responsible for leading the research agenda of the Science of Quantum and Information Technology department aiming to create scientific and technological breakthroughs in Quantum Computing, Physics of Artificial Intelligence, Nanoscience and Nanotechnology, Precision Diagnostics and Smart System Integration.
She is a distinguished expert in nanotechnology and nanosciences and focuses her research on advancing the frontiers of information technology through the physical sciences. She contributed to advancements in the science and technology of nanoscale electronics, in particular the exploration and development of semiconducting nanowires and nanostructures for applications in future electronic and optoelectronic devices, in molecular electronics for future nanoscale switches and memory applications, and organic light-emitting diodes for display applications. Her current research interests include new materials and device concepts for future nanoelectronics for applications in quantum computing and neuromorphic computing. She also serves as the Deputy Director of the new Swiss National Competence Center for Research on Silicon Spin Qubits.
Event Details FORMAT: General session with live audience Q&A to follow each presentation.
MENU: Coffee, decaf, and tea will be available outside presentation room.
SETUP: Theater style seating.