8:00 AM - 8:10 AM:
Welcome and opening remarks
Qinghuang Lin, Canon Nanotechnologies, Inc. (United States); John C. Robinson, KLA Corp. (United States)

 

8:10 AM - 8:15 AM:
SPIE Frits Zernike Award for Microlithography
Presented in recognition of outstanding accomplishments in microlithographic technology, especially those furthering the development of semiconductor lithographic imaging solutions.

 

8:55 AM - 8:20 AM:
Presentation of the Nick Cobb Memorial Scholarship
The Nick Cobb Memorial Scholarship is awarded to an outstanding graduate student studying advanced lithography or a related field. The scholarship is jointly funded by Siemens EDA and SPIE.

 

8:20 AM - 9:00 AM:
Riding the wave of AI with semiconductor technology innovations

Michael Wu TSMC (Taiwan)

The rapid evolution of generative artificial intelligence has attracted unprecedented global attention and is changing the future of the workplace and the development of the industry. The effective use of generative artificial intelligence has also become an indispensable competitive advantage for enterprises in digital empowerment. Continuous innovation and breakthroughs in semiconductor technology are undoubtedly one of the important enablers of the development of artificial intelligence.
The exponential growth of chip computing power is the best manifestation and contribution of the continued progressof semiconductor technology scaling. In the next five to ten years, the application of artificial intelligence will become a new growth driver for the semiconductor industry. The symbiotic relationship between artificial intelligence and semiconductor technology will further bring unparalleled maximum synergy to the development of society.
In this paper, we will review the evolution of artificial intelligence and the advancement in CMOS technology. In addition, examples of machine learning assisted technology development will be illustrated. Looking forward, the anticipated process technology challenges and opportunities will also be discussed.

Dr. Michael Wu is Vice President of Platform Technology Development under Research and Development (R&D) at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). He is currently responsible for advanced platform technology development and is also in charge of TSMC’s Technology Development Effectiveness Office. Dr. Wu joined TSMC R&D in 1996 and has since participated in advanced CMOS technology development from 0.13um, 90nm, 65nm to 28nm, and contributed greatly to successful development of 16nm, 7nm and 3nm technologies.
Dr. Wu has received multiple recognitions including the National Industrial Innovation Award – Innovative Trailblazer of the Year in 2013, the National Management Excellence Award in 2015, and the Chinese Outstanding Engineer Award in 2017.
Dr. Wu served in several positions in the Executive Committee of the International Electron Devices Meeting (IEDM) from 2013 to 2016 and was Technical Program Chair and General Chair of VLSI-TSA in 2017 and 2018, respectively.
Dr. Wu was inducted as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for his leadership in CMOS process integration. He has published 50 papers and holds a total of 72 patents in the field of semiconductor technology.
Dr. Wu received his M.S. degree and Ph.D. in Electrical Engineering from University of Wisconsin-Madison. He also received an EMBA degree in the Institute of Technology Management from National Tsing Hua University.

9:00 AM - 9:40 AM:
Strategic directions for electronics packaging

Subramanian S. Iyer UCLA Center for Heterogeneous Integration and Performance Scaling, Samueli School of Engineering (United States)

Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in Artificial Intelligence and Machine Learning that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of “scale-down and scale-out” that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. While, we have made progress towards this goal, the technologies we have developed have ridden on legacy packaging technologies making such systems incredibly complex and expensive to build. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically. There are many challenges in this approach. In this talk we will outline these challenges especially in lithography and die placement and show that the adoption of silicon like technology, new cooling and power delivery, large area lithography approaches, as well as design enablement will propel packaging into the next dimension.

Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. Till recently, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging Manufacturing Program, where he laid the foundational strategy for the national packaging imperative. He is the founding Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. Since joining UCLA, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He is a fellow of IEEE, APS, iMAPS and NAI as well as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPS distinguished educator award in 2021. Prof. Iyer was also Prof. Ramakrishna Rao Visiting Chair Professor at IISc, Bengaluru.

Event Details

FORMAT: General session with live audience Q&A to follow each presentation.
MENU: Coffee, decaf, and tea will be available outside presentation room.
SETUP: Theater style seating.