Chip manufacturers discuss advanced lithography challenges and solutions

In two Tuesday plenary presentations at the 2024 SPIE Advanced Lithography + Patterning conference, representatives from Intel and Samsung, leading suppliers of logic and memory chips, outlined where they see lithography, patterning, and semiconductor manufacturing headed. Both speakers noted that the past provides important guidance.

One reason is that the expected trajectory of the semiconductor industry follows what has happened previously, with more transistors historically being on chips leading to increased device functionality and performance. For example, the transistor count on an advanced device stands at a little more than 100 million.

“We’re on track to hit a trillion transistors in a packaged product by 2030,” said Anne Kelleher, executive vice president and general manager of technology development at Intel, in her presentation.

That projection for at least a 10-fold increase is in line with the historic trend, which has seen transistor count on a device grow from 1000 in 1970 to hundreds of millions today.

But continuing that path requires innovation in new areas. In her talk, Kelleher pointed out that initially the industry engaged in geometric scaling, shrinking feature sizes of transistors on chips through improved lithography and patterning. Then the industry turned to DTCO, or design-technology co-optimization. DTCO resulted in changes to the layout of standard cells on chips and blocks of cells.

Kelleher predicted that the trend will be for system technology co-optimization. Chip and tool makers will continue silicon scaling through the rollout of high NA EUV, the next step in high volume advanced lithography. As proof of progress toward that goal, she proudly showed the first light from an ASML high NA production tool, likening the test pattern on the wafer proving tool capabilities to images of bananas. One of the high NA EUV machines is being installed at an Intel fab, the first such tool installation in the world. Kelleher said Intel will do product proof points demonstrating that the tool is ready for manufacturing in 2025.

That development will join layout advances such as putting the power carrying metal traces on the back of the chip and the signal carrying metal on the front. Doing so should result in a 10 percent increased utilization of chip area, a six percent improvement in performance, and a four percent reduction in switching energy, Kelleher said.

Additional progress is possible with heterogeneous integrated circuits, devices built up of what in the past would been individual chips. New packaging technology makes this possible, a system optimization that should cut power consumption five hundred times.

This capability requires significant improvements in packaging, the encapsulation of a finished chip in a container that protects it while allowing the device to connect to the outside world. Kelleher noted that in a few years the length scale of the package may be about the same as that of the top level of metal on a chip. This convergence is a sign of an erasure of what in the past has been a firm divide between wafer fabrication and the packaging that follows.

“The line between silicon and advanced packaging is blurring,” Kelleher said. “Where does the fab stop and packaging start?”

In his presentation, Chan Hwang, who leads memory process development at Samsung’s R&D center, first started with a history lesson. He recapped the past 20 years of advanced lithography technology with a focus on deep ultraviolet, or DUV, lithography. Today’s lithography king is extreme ultraviolet or EUV. But the past evolution of DUV shouldn’t be ignored or forgotten.

“I think EUV will follow the path of DUV lithography,” Hwang said.

If that proves to be the case, then there will be a series of improvements to several areas, with these intended to enhance the uniformity and accuracy of the final pattern on the wafer. There will be some modifications to what was done before, though, due to differences between DUV and EUV.

As Hwang noted, there are 14 times fewer photons in an EUV exposure as there are in a DUV exposure, a consequence of the greater energy in each EUV photon compared to a DUV photon. Thus, these smaller photon numbers lead to more random variations. These stochastic effects play a significant role in EUV lithography, leading to a greater chance for discrepancies in the printed pattern from the ideal.

Hwang said there needs to be co-optimization of the printing process, which puts the pattern in the photoresist on a wafer, and the etch process, which selectively removes material. Such coordinated innovation can overcome some of these stochastic impacts. Similarly, there will need to be improvements mask making, along with other innovations, according to Hwang.

It was evident in both talks that lithography and patterning need to expand their horizons and improve their capabilities. There are many areas to do so, ranging from wafers to masks to packaging.

As Kelleher said near the end of her presentation, "There are lots of opportunities for lithographers and anybody who's in patterning."

Hank Hogan is a science writer based in Reno, Nevada.