Photonics aids the march of Moore's Law

Imagine technology development without Moore’s Law, where the doubling of device transistors every two years ceases. In this scenario, a smartphone bought five years from now would have no more processing power, memory storage, and connectivity speed than today’s models. Data centers a decade hence will balloon even more in size, because they will need many more servers to perform the computationally heavy tasks demanded by AI. Even cars, 20 years into the future, won’t be any smarter than today’s.

Avoiding this technical stagnation depends on Moore’s Law. Industry insiders say the trend of ever-increasing transistor counts will continue. Today’s devices top out at 100 billion transistors on a single piece of silicon. TSMC, the Taiwanese silicon foundry giant that makes devices for Apple, Nvidia, and others, believes products with more than 10 times that number will be here within this decade.

That’s a target Intel set in a 2022 presentation, and at the mid-point of the decade it’s still the goal, according to Sanjay Natarajan, senior vice president and general manager of Intel Foundry Technology Research. “Intel is still on the path to delivering one trillion transistors on a package by 2030.”

Part of the advances needed to keep Moore’s Law going involve photonics. First, there’s photolithography, for decades a key driver for semiconductor manufacturing advances. Second, there’s optical networking at the device level, a new application for photonics.

Regarding photolithography, there was a long phase in which transistors underwent a geometric shrink, says Kirk Bresniker, chief architect and vice president at HP Labs. Device fabricators would in effect turn a dial and reduce the size of transistor features, bringing benefits in transistor parameters.

“Not only did they get cheaper, they ran faster and used less energy,” Bresniker recalls.

The increase in transistor density since Moore’s Law was formulated in the mid-1960s came from the movement from one “technology node” to the next. The technology node was 20 µm in 1968, and this year the 2 nm node is slated to go into commercial production.

In the beginning, the technology node referred to the smallest critical feature size, such as the width of the gate that controlled electron flow in a transistor. Today, the designation refers to the equivalent size. In 1968, device transistor count was under a thousand. Now, it stands at 100 billion. That increase implies a physical dimension shrink of 10,000, which would be expected with a move from 20 µm to 2 nm technology nodes.

Currently, transistor density continues to climb. However, related improvements in speed, power, and cost are not as great node-to-node as they once were. What’s more, there are applications of semiconductors, like mobile devices or automobiles, that didn’t exist as markets decades ago.

Addressing the performance slowdown and broader application range are reasons the semiconductor industry and academia have been collaborating since 2016 on the International Roadmap for Devices and Systems (IRDS). Roadmap teams produce predictions about likely developments in electronic devices and systems over the next 15 years, highlighting areas that need work and concerns that should be addressed. Members are drawn from the US, Europe, Japan, and South Korea. Bresniker co-chairs the systems and architectures chapter of IRDS.

Some of the issues highlighted by IRDS are due to material challenges. Other issues arise from photolithography difficulties.

When considering photolithography, it helps to see it in a semiconductor context. Chip fabrication involves deposition or growth of a layer on a wafer, usually silicon. Once the layer is in place, manufacturers put photoresist material on the wafer. Using a photolithography machine, fabricators then have a light source interact with a mask to transfer a circuit pattern to the wafer.

A wafer is processed in a semiconductor fab. Photo credit: Taiwan Semiconductor Manufacturing (TSMC).

For example, the mask may contain the pattern of connections that will ultimately wire transistors together in the finished product. After undergoing photolithographic and subsequent processing, the wiring pattern will exist as metal lines on the wafer, with this pattern precisely aligned to the layout of existing circuit elements already on the wafer. Devices may go through hundreds of lithography steps as transistors and circuits are built up piece by piece.

The feature size limit to photolithographic printing is tied to the wavelength of the light source. A shorter wavelength source enables the patterning of smaller features than would be possible with a longer wavelength source, given equal optics performance.

The light source wavelength for today’s most advanced lithography is 13.5 nm, with these extreme ultraviolet (EUV) photons generated by bombarding a tin droplet with a powerful infrared pulse from a CO₂ laser to create a plasma that radiates EUV light. The production of EUV photons happens 50,000 times a second, according to lithography tool maker ASML.

Natarajan notes that advances in lithography are critical for continuing Moore’s Law and reaching the one-trillion-transistor mark. In addition to using a shorter wavelength, another way to print smaller features is by enhancing the system’s ability to resolve fine details, which is measured by the numerical aperture (NA). Current EUV machines have a 0.33 NA, while EUV machines with a high 0.55 NA have just been developed.

“Another key enabler will be high-NA EUV lithography, which can enable significant improvements in resolution and transistor density,” Natarajan says.

More advanced machines with an NA of 0.7 or greater are under consideration. But such development is costly in both time and money. So, semiconductor device fabricators are exploring other avenues to increase transistor density.

One approach is to use chiplets, specialized chunks of electronics that sit inside a device package and perform specific functions. Together, chips and chiplets, to the outside world, make up what appears to be one device.

TSMC says chiplets will play an essential role in hitting the 1-trillion transistor-device mark. That’s because going the chiplet route solves a problem. There is an upper limit to mask size in photolithography machines, and with current technology, fabricators can only fit in about 100 billion transistors in a maximum size mask.

According to TSMC, chiplets placed side by side or stacked on top of each other in the same package help them reach a much higher transistor count per system, compared with what can be squeezed into one silicon die.

In the past, device designers wanted everything on a single silicon die because that offered much faster and more energy efficient connections. Today, technological advances make breaking up a device into chiplets acceptable because there’s no longer a significant performance hit.

To achieve this feat, the connections between the various chiplets must be short and densely spaced, as this minimizes the distance a signal must travel and thus reduces any performance hit. Using chiplets makes it possible to achieve both device density and performance. The divide-and-conquer approach also offers other benefits, notes Akshay Singh, vice president of advanced packaging technology development at Micron Technology.

The doubling of device transistor count, Moore’s Law, will result in chips having had a few thousand transistors in the early 1970s, to as many as a trillion in 2030.

“You can look at it like Lego blocks. You make each of these things separately and then use advanced packaging to stitch them together,” he says. “Advanced packaging is being viewed as something that will allow us to continue to scale.”

One chiplet, for example, could be optimized for processors. Another could be for memory. A third type could involve sensors or other analog-integrated circuits. A fourth chiplet might provide electronics or silicon photonics for communications. All would be built on wafers that are hundreds of microns thick, using advanced packaging techniques that tie the various chiplets together with short run metal.

Older packaging methods might run a wire from the chip out to the package, a long round-trip distance that significantly constrained signal speed and performance. Advanced packaging avoids this problem through such techniques as punching tiny holes through the silicon, filling those holes with copper, and connecting those conductive pathways to other pieces of silicon through bumps and pads.

At semiconductor research center imec, teams are working on the next step beyond chiplets, according to R&D Vice President Julien Ryckaert. Dubbed CMOS 2.0, their idea leverages the ability to connect stacks of roughly 200 nm thick silicon together.

Each thin slice will be built using technology that is best for its specific function, and all will be tied together electrically in a way that makes it look like they are all components of a single chip built the traditional way.

This next-generation manufacturing method brings lithography challenges. For example, lithography today is done on a comparatively thick and rigid wafer that can measure, in the case of silicon, up to 300 mm across and 0.775 mm thick. With the stack approach, fabricators will be dealing with what amounts to a thin and deformable pancake.

“You’re going to flip front to back because every layer now has a requirement for connectivity that is seamless whether it’s connecting up or down,” Ryckaert says.

This thin slice layer approach and necessary manipulation will make photolithography difficult, Ryckaert says, and teams at imec recognize the concern and are developing solutions.

One issue that looms over all 3D stacks of semiconductor circuitry is how to get power and input signals into such a block, as well as how to get heat and output signals out. Here, the emerging application of silicon photonics at the device level can play a role because it can reduce the power needed and waste heat produced.

Today, communication connections longer than a few meters use photons instead of electrons, Bresniker says. Thus, in a large high-performance computer like those found in a data center,  the racks communicate over optical fiber, but data transfers between chips and within chip packages use electrons.

Chipmakers are working to bring photonic connections into their circuit boards and devices because photonic connections are more energy efficient. Intel says optical links will become increasingly important as more chiplets go into each package, and the distances between them grow greater, because going to photon-based communication is more energy efficient.

That view of the importance of silicon photonics is shared by other fabricators. TSMC is developing a technology that stacks an electrical die on top of a photonic die using its proprietary 3D chip-stacking process, a spokesperson says. Scheduled to debut in 2026, the technology will support the growth in data-transmission needs driven by AI. The company claims its technology will reduce power needs by a factor of four, cut delays in data transfer by an order of magnitude, and enable a smaller overall form factor that may make it possible to shrink the size of boards.

Silicon photonics manufacturing uses lithography, similar to the fabrication method of electronic computer chips. There are, though, some important differences, points out Joris Van Campenhout, imec’s research and development program director for optical I/O. For instance, the critical feature sizes in silicon photonics are in the hundreds of nanometers, larger by several orders of magnitude than the finest features of the most advanced semiconductor chips.

At the same time, though, tight control of feature dimensions is needed in silicon photonics manufacturing. A 1 nm change in the average width of a waveguide from one to the next can lead to a 100 nm drift in the wavelength response between the two waveguides. Such a drift, in turn, can limit the communication rate of a data link. Van Campenhout notes that while silicon photonics chipmaking does not demand technology as advanced as an EUV machine, the fabrication of optical components nonetheless requires care.

As for how the optical components might be manufactured, he says that some of the materials being considered, like lithium niobate thin film modulators, require special handling. Even miniscule amounts of such compounds will poison standard semiconductor electronics and degrade performance.

However, there might be a way to process such problematic materials while protecting sensitive semiconductors and cutting costs. It would involve fabricating waveguides using an electronics-compatible process but then taking the wafer to a separate fab for the remaining steps such as the ones that involve putting lithium niobate where it needs to go.

“We’re going to take that wafer out and then we’re going to do that ‘dirty’ processing, maybe in a separate fab where you don’t need all this expensive equipment,” Van Campenhout says.

Looking to the future, photonics will play an important part in any continuation of Moore’s Law. Mikael Östling is an electrical engineering professor at the KTH Royal Institute of Technology who investigates power semiconductors. He also coordinates the IRDS More-than-Moore activities, which focus on sensors, power devices, and microelectromechanical systems. He notes that scaling semiconductor devices continues, as does the incorporation of new functionalities, two areas with important photonics contributions.

As for further progress, silicon can do wonders, but silicon alone won’t be enough. Fabricators today already use a myriad of materials, according to Östling. On the horizon are 2D materials like graphene and carbon nanotubes that have the potential to boost performance and allow Moore’s Law to continue.

 The key, though, is not what can be done in limited numbers in a lab. It’s what can be made in volume and for the right price in a product that improves upon what is available. “Can you fabricate something that is viable from an economical point of view?” Östling asks.

Intel’s Natarajan agrees that Moore’s Law isn’t simply about packing more transistors into a device. The increase in density must also be affordable. The cost of a processed wafer goes up from node-to-node, and so the benefits of the new technology must be great enough to offset the cost increase.

A time will come when that tradeoff does not make economic sense, and Moore’s Law will end. Industry insiders are betting that is not yet the case. Natarajan lists imminent or planned advances, like putting power supply circuitry on the back of wafers to free up space on the front, using glass substrates to overcome transistor scaling problems, and innovations in transistor design.

“The death of Moore’s Law has been predicted for decades,” he notes. “Moore’s Law will only stop when innovation stops, and we see no end in sight.”

Hank Hogan is a freelance science and technology writer.