Panel discusses the future of EUV

01 March 2024
Hank Hogan
A panel representing all aspects of the lithographic ecosystem on the future of EUV lithography at 2024 SPIE Advanced Lithography + Patterning
A panel discussion at SPIE Advanced Lithography + Patterning on the future of EUV lithography. From left to right: Mark Slezak, JSR (Japan); Jan van Schoot, ASML (Netherlands); Emily Gallagher, imec (Belgium); Frank Abboud, Intel (USA); Youngseog Kang, Samsung (RoK); and Andreas Erdmann, Fraunhofer IISB (Germany).

A panel representing all aspects of the lithographic ecosystem talked about the future of EUV lithography late Wednesday during the 2024 SPIE Advanced Lithography + Patterning conference. Their outlook about EUV’s prospects varied widely.

Mark Slezak, president of photoresist supplier JSR USA, was bullish. “I think we have a 20-year runway,” he said.

This long lifetime for EUV is based on history. The industry used DUV lithography, EUV’s predecessor, for much longer than anyone thought possible. Innovations such as immersion lithography and the use of multiple passes through scanners to pattern finer features extended the lifetime of the technology. Users could deploy similar techniques to extend EUV’s usefulness, with some innovations already in the works. High NA EUV, for example, if it performs as planned, could be one avenue to such an extension.

Others on the panel, however, do not foresee such a long lifetime for EUV. Young Seog Kang, a Fellow at Samsung, is involved in the memory chip maker’s lithography. He predicted that EUV will have a short useful lifetime because the proposed ways to extend the technology will run into performance and cost issues.

“As a user, I'm always concerned with total cost,” he said.

Kang pointed out that low-NA EUV is already up and running. Chip makers could implement double patterning using that version of EUV instead of a more expensive alternative. What’s more, chip suppliers are turning to advanced packaging and other means to produce chips. Thus, users will have alternatives to high-NA EUV that might turn out to be less expensive once all factors are considered.

Kang did say that EUV might have a short duration for memory chips, which have vast arrays of repeating cells. But, he added, EUV might stick around much longer for logic chips because the layout of those devices is much more random.

Others on the panel fell between these two extremes. Frank Abboud, vice president and general manager of mask operations at Intel, noted that phase shift masks proved very beneficial in DUV and helped extend the life and capability of the technology. Such masks use interference generated by phase differences to improve image resolution. Phase shift masks haven’t yet been produced for EUV lithography, but they could be.

“So far it appears to be doable,” Abboud said.

Jan van Schoot, director of system engineering at lithography tool maker ASML, noted that there are several knobs to turn to improve resolution and extend EUV’s usefulness. One is the numerical aperture, with resolution going up as this is increased. Another is called k1, a coefficient that depends on many factors related to chip manufacturing.

There’s already work underway to up the NA of EUV, which today stands at 0.33. The first high-NA tool, which has 0.55 NA, is now in place. But little has been done to address k1. According to van Schoot, ASML is working on a new illuminator and taking other steps to improve k1.

“We don’t have all the solutions, but we have some promising ideas,” he said.

EUV’s current illumination technology is quite different than that of DUV, which used an excimer laser. The resulting beam featured a tight profile spatially and spectrally.

“Having a smaller bandwidth, that would be useful,” said Andreas Erdmann, group manager of computational lithography and optics at Fraunhofer IISB, in talking about desired improvements to EUV illumination technology.

Finally, the long-term outlook for EUV may be decided by something outside of the technology itself. Emily Gallagher, principal member of the technical staff at imec, noted that EUV in the future might run into resource constraints and environmental roadblocks of various kinds. For instance, fluorine-containing gases can be powerful contributors to greenhouse gas emissions, with some having tens of thousands of times the effect of carbon dioxide. The industry is working to eliminate fluorine but doing so may involve requalifying processes with substitutes, which will take some time.

Consequently, the industry may have to figure out ways to abate the fluorine emission, either by destroying the gas through incineration or other means or by capturing it. Such abatement is getting easier to do, in part because chip makers aren’t the only ones who face the need to use fluorinated gas but not let it escape into the environment.

“There are more and more solutions being developed,” Gallagher said of abatement.

She then added, “There’s an advantage to looking outside the semiconductor industry.” 

Hank Hogan is a science writer based in Reno, Nevada.

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