Nanoimprint lithography coming into its own

Many of the lithographic advances discussed at the 2024 SPIE Advanced Lithography + Patterning conference concern projection approaches, with light interacting with a photomask and exposing photoresist on a wafer at a distance. But there are other techniques, such as nanoimprint lithography. It is attracting attention, as illustrated by two Tuesday afternoon presentations from the conference.

Toshihiro Ifuku of Canon gave the first talk, summarizing the company’s work with its FPA-1200 NZ2C tool and performance improvements in nanoimprint lithography. This form of lithography is of interest because it offers the ability to produce nanometer sized features at high throughput and low cost.

Canon has used its tool to make meta optical elements, an application that is now achievable due to advances in nanoimprint lithography performance. Meta optical elements could be useful in phones, cameras, and other devices that use shaped lenses to focus light for imaging or other applications.

“With the introduction of metal optical elements, it becomes possible to shrink lenses and remove constraints,” Ifuku said.

As the name implies, nanoimprint lithography involves physically pressing a template into resist on a wafer and then freeing the template from the resist, which remains behind to act as a mask for subsequent etching and other processing. Canon’s nanoimprint tool uses field-by-field deposition and exposure of a low viscosity resist placed as droplets onto the substrate. The tool squirts resist droplets onto a wafer, presses a template into it, exposes the resist, and frees the template. It repeats the process for the next field, continuing these steps until the entire wafer is covered.  

In addition to the tool, Canon has been developing the supporting ecosystem needed to bring nanoimprint lithography into production. Ifuku reported, for example, that the company has created a simulator software used to ensure that droplet recipes will work for a given use.

Another application of nanoimprint lithography could be in the making of DRAM memories, as detailed in a presentation by Tomohiro Iwaki, a lithography principal engineer at Micron Memory Japan. Iwaki noted that DRAMs tend to face intense cost pressure and so cutting manufacturing expenses can be critical. Nanoimprint lithography doesn’t require costly lenses or an expensive light source and so it could complement EUV manufacturing by taking over the fabrication of those layers that are less demanding.

Today, the alternative to EUV is DUV, a lithographic technology that was the workhorse of semiconductor manufacturing for years but now surpassed by more capable EUV. DUV lithography still patterns those layers with less exacting requirements.

However, as DRAM feature sizes continue to shrink, DUV faces challenges in being able to produce the metal lines and spaces. Nanoimprint lithography can fabricate down to a 40-nanometer pitch, a figure that puts it between DUV and EUV in terms of capability, Iwaki reported.

“NIL [nanoimprint lithography] is a technology that complements the resolution of EUV and DUV,” Iwaki said.

The new technology has problems, such as issues where the roughness of the edge cut leads to silicon voids that are filled by metal during deposition. There also can be blowouts — defects that look like the intended pattern suffered something akin to a tire puncture. Changes in the layout that involve adding features, Iwaki said, would reduce or eliminate these issues. Misalignment of the nanoimprinted layer to earlier layers and tight overlay margins between layers cause these problems, Iwaki theorized. Such situations show up only a small number of times in a typical layout.

The technology can already meet the general overlay requirements for the tightest pitch, Iwaki said in a Q&A after the presentation. Defect levels still need verification. Another issue could be the cost of the nanoimprint masks because these have a more limited lifetime than projection lithography masks.

Micron Memory is not the only company looking at using nanoimprint lithography for memory fabrication. In addition to demonstrating the usefulness of the technology in making meta optical elements, Canon also demonstrated that nanoimprint lithography is suitable for backend-of-the-line processing, such as would be needed for fabricating the last metal layer in memory chip.

A backend-of-the-line fabrication application requires the right overlay and critical dimension control of features as well as low defectivity in the lithography process. In a Q&A session after his talk, Canon’s Ifuku said that most of the defects seen during Canon’s evaluation of the technology did not come from the nanoimprint lithography process but were instead already on the wafers coming into the tool. Hence, cleaning the wafers could remove the defects and make the nanoimprint lithography more attractive.