Innovative ways to make and measure nanostructures

01 March 2024
Hank Hogan
A slide from Tomohiro Goto's (Kioxia Corp) talk at SPIE Lithography + Patterning on wafer bonding technology.
A slide from Tomohiro Goto's (Kioxia Corp) talk at SPIE Lithography + Patterning on wafer bonding technology.

Fabricators of nanometer scale structures must be able to make and measure them. Those challenges force innovative solutions, as seen in a trio of 2024 SPIE Advanced Lithography + Patterning conference presentations.

On Tuesday, Tomohiro Goto, a memory development specialist at Kioxia Corp., discussed wafer bonding measurements. In advanced devices, the memory is built on one wafer while the logic is fabricated on another to optimize the manufacturing of each. Device makers bond the two wafers and electrically connect them.

“Wafer bonding technology is one of the key processes for high-density and high-performance semiconductor devices,” Goto said.

Manufacturers must align the two wafers and bring them together with a high degree of precision. Checking the overlay between the two wafers has traditionally used visible light. However, since silicon absorbs the light, device manufacturers thin the wafers. Only after that can fabricators make a measurement of overlay.

Goto reported on a project by Kioxia to use infrared light, which passes through silicon. Comparing the infrared and visible results showed good measurement repeatability and accuracy. For wafer bonding applications, the use of IR enables measurement right after wafer bonding. Kioxia used this data on how good the bonding was in a feedback loop to improve process control of the bonding process, raising process yield and performance.

In a paper presented Wednesday morning, Jong-Gu Lee, a staff mechatronics research engineer at Samsung Electronics, discussed what happens when bonding wafers. Wafers that appear flat to the eye are anything but in the microscopic world. Films put down and removed during processing as well as heat cause hills, valleys, and other distortions on the micron and nanometer scale. These deviations grow when two wafers are mechanically bonded.

“After the bonding process, the deformation becomes more complex,” Lee said.

Part of the reason for this behavior lies in the basic nature of the wafer. The silicon is crystalline, with the (100) orientation the one most used because it offers easier processing. However, that orientation reacts to mechanical strain differently depending on the direction of the force. In contrast, silicon with a (111) orientation responds the same no matter where the force is applied.

So, Lee and his co-workers proposed a hybrid wafer: a thick (111) wafer with a thin (100) wafer atop it. They designated these Angle-ply Laminating Wafers and developed a model to simulate them. Calculations indicated a significant reduction in the distortion from the mechanical effects of bonding, which should improve the overlay margin for devices built on such hybrid wafers.

During a Q&A after his talk, Lee noted that these results are for simulation only. Eventually, researchers will need to build hybrid wafers and confirm the simulation results.

A final set of innovation examples formed the basis for a presentation by Gian Lorusso, principal scientist at Imec, about trends in e-beam metrology and inspection. E-beam, or electron-beam, systems have been used for decades in wafer fabrication because they enable the inspection and measurement of very small features, a consequence of the extremely short wavelengths of electrons.

However, up until recently the applications of e-beams inside a wafer fab were limited. That’s changed, Lorusso said, because the fabrication process needs have changed.

“The requirements are getting tighter and tighter. We are getting smaller and smaller features to measure,” he said.

In response, researchers are figuring out new ways to use e-beam systems. For instance, the latest EUV lithography uses a very thin resist. Using the standard e-beam landing energy on thin resist leads to a loss of contrast. Switching an e-beam system to a low-landing energy beam, though, gets around this problem.

But, Lorusso noted, a high-landing energy beam can extract a lot of parameters about the 3D structure of a semiconductor. Thus, being able to adjust the landing beam energy — and knowing when to do so — pays off with the measurement data needed to ensure correct chip fabrication.

There are other adjustments that enable an e-beam system to accomplish what an atomic force microscope can do. An advantage of this approach is that an e-beam system can acquire the data 100 times faster.

Speaking of speed, Lorusso pointed out that e-beam systems are still significantly slower than an optical inspection system. One work around under development is a multi-beam approach, a method in which a system uses many beams to scan a wafer’s surface.

In a Q&A session after his talk, Lorusso said that the goal of high-volume, high-speed inspection using e-beam technology is likely feasible. He added this was particularly the case given the demands for improved inspection.

“We’re going to get there because we need to get there,” he said.

Hank Hogan is a science writer based in Reno, Nevada.

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