Improving EUV lithography

The work of improving and extending EUV lithography isn’t done. Three presentations at the 2024 SPIE Advanced Lithography + Patterning conference provide examples of such efforts.

On Wednesday, Keiyu Ou, a materials researcher at FUJIFILM, presented a new developer. In semiconductor lithography, chip makers coat a wafer with photoresist, expose that resist selectively using a mask, bake the resist to harden it, and then use a developer to make the resist disappear where exposed in the case of positive tone resist or unexposed in the case of a negative tone resist. The result is a pattern on the wafer for subsequent etching of the underlying film and other processing.

According to Ou, FUJIFILM’s initial deployment of its developer in an EUV trial didn’t work because there were too many defects, points where lines that should be separate touched or features that should have been present weren’t. That outcome caused the research team to adjust its approach.

“Further stochastic reduction should be taken,” Ou said in describing this new goal.

The stochastic, or random, events causing the problems were rooted in the chemistry of the developer, Ou said. The researchers investigated the mechanism behind these defects and concluded that the issue was swelling of the resist during the development process. So, they adjusted the developer’s formulation, adding a proprietary hydrophobic solvent. Such a solvent tends to not mix with water, and this change in the formulation allowed the developer to handle lines and spaces as low as 28 nm pitch, suitable for use in the EUV technology version just going into high-volume manufacturing.

In another example of ongoing EUV improvements, on Thursday morning Jara Garcia-Santaclara, EUV High-NA product manager at ASML, reported on progress in delivering a high-NA imaging tool. She noted that simply achieving the required resolution isn’t enough.

“Not only is resolution important for our customers but also the performance we deliver at that resolution,” she said.

Making a high-NA system was a decade long process, with design of the tool starting in 2014 and the first one delivered to a customer Q4 2023. ASML used as much technology as possible from its low-NA product. The company also did research and development aimed at solving those issues arising from high NA itself.

One of these is the size of the field of view. The switch from low-NA systems, which have a numerical aperture of 0.33, to high-NA systems, which are 0.55 NA, results from the need to improve resolution. If everything else is equal, a high-NA system can produce an image 40 percent smaller than with a low-NA system.

But that higher NA also reduces the field of view, which means it’s not possible to image an entire large die at once. To overcome this problem, the industry plans to deploy stitching, a technique in which two mask exposures pattern separate halves of the chip with a small overlap of the halves. Stitching, though, requires exceedingly fine control of exposure intensity and very tight precision of the exposure placement. If that’s not done, then the stitched area is defective, and the chip won’t work.

Garcia-Santaclara showed good stitching results, verification of a needed capability. She also noted progress in many other areas, such as resists and other materials.

A third example of ongoing improvements came in a presentation on Thursday by Robert Browning, process TD engineering group leader at Intel. He discussed a way to advance EUV patterning though pattern shaping. This technique, he explained, takes a pattern printed on a wafer and stretches it, doing so only in one direction by using a masking step and angled etch.

In presenting an example of this, he said, “We elongate only in the y-direction and not in the x.”

After going through one pass, rotating the wafer and going through another pass ensures the stretch occurs equally to both sides. With this method, features may expand by 20-nanometers or more in y but nothing in x. Thus, what starts as a square may become a rectangle and what in the original pattern is a circle becomes an oval.

The x- and y-directions for this elongation depend on wafer orientation at the start of the process. Because of this, the elongation direction is arbitrary, and chip makers can adjust this stretching direction and extent to reap the greatest benefit.

Chief among these is the ability to extend patterning capabilities below what is possible with EUV lithography because pattern shaping can clean up rough line edges. Pattern shaping can also help eliminate EUV lithography steps.

The savings in time and costs are significant, Browning said. “The numbers can add up substantially.”

Hank Hogan is a science writer based in Reno, Nevada.